In recent years, as an element isolation structure in an LSI device, an STI (Shallow Trench Isolation) structure has been adopted that enables dimensions of an element isolation region to be controlled with high accuracy, as a substitute for a LOCOS structure. The STI structure is an element isolation structure that is formed by forming a shallow trench with an almost perpendicular side wall in a semiconductor substrate and embedding an insulating layer in the trench and that is suitable for high-integration LSI.
The importance of rounding an upper corner portion in forming a trench has conventionally been pointed out (for example, JP 2000-299374).
In other words, when an upper end portion (shoulder portion) of a trench formed in a semiconductor substrate is not rounded and remains a shape with an acute angle, the possibility of causing following inconvenience increases.
Concentration of an electric field tends to occur. The embedding characteristic deteriorates when an insulating layer is embedded in the trench, and a void tends to occur inside the trench (particularly, near the surface of the trench). Further, the leak current tends to occur in the upper end portion of the trench.
Further, such inconvenience tends to occur that an insulating layer embedded in the trench rises in the upper end portion of the trench, thereby loses the flatness, and has an adverse effect on a conductive layer provided on the insulating layer.
Therefore, methods have been proposed of rounding the shoulder portion of the trench. Related art in Patent Document 1 describes a method of forming a sacrifice oxide film and removing the film and another method of optimizing a composition of etching gas and etching conditions.
Further, in above-mentioned JP 2000-299374, a mask in an inverse-tapered specific shape is formed as a trench processing mask, and using the mask, the corner portion of the trench is rounded.
Furthermore, the applicant of the present invention previously proposed an anisotropic oxidation technique of halogen-oxidizing an internal portion of a trench using dichloroethylene (DCE: C2H2Cl2), and by this halogen oxidation, making the thickness of the oxide film in a shoulder portion of the trench thicker than the thickness of the oxide film in the other portion in the trench (JP 2004-228457).
With further progress in fine patterning in LSIs, the width of the trench is made narrower. With the narrowed width, it is made difficult to embed an oxide film (insulating film) uniformly in the narrow trench, and a void tends to occur.
The void is apt to be a source of generating foreign substances. When the void is exposed at the surface of the wafer with the insulating film polished, the risk increases that a short circuit occurs in wiring, or some adverse effect is imposed on wiring.
In order to prevent the occurrence of a void in the embedded insulating film, it is effective to round a corner of a shoulder portion of the trench to broaden an opening. However, among methods described in above-mentioned JP 2000-299374, in the method of removing a sacrifice oxide film, the effect of processing of rounding a corner portion is small in a single time, and formation and removing of the sacrifice oxide film needs to be repeated over a plurality of times. Accordingly, there are fears that the process is complicated and that damage in the trench is accumulated.
Further, in the method of rounding a corner portion of the trench while varying a composition of etching gas and etching conditions, the effect of rounding is not so significant, and the embedding characteristic of the insulating film in the fine trench is not greatly improved.
Furthermore, as the fine patterning in LSI proceeds, the size decreases of an insulating gate type field-effect transistor packed in a semiconductor substrate, and with the decrease, the current capability decreases in the transistor. With consideration given to the fact that the STI and transistor are disposed adjacent to each other, in forming shallow trench isolation (STI), it is important to also consider the effect of improving characteristics of the transistor (i.e. consider the method of forming STI in terms of improving characteristics of the transistor), but the above-mentioned STI forming method lacks this point of view.
The present invention is carried out in the view of the above-mentioned consideration, and it is an object of the invention to sufficiently back off a shoulder portion (upper end portion of an opening) of the trench while adequately rounding a corner portion to broaden the opening in a single time of processing, and implement an excellent embedding characteristic of an insulating film filled in the trench to prevent the occurrence of a void. It is another object to assure high-accuracy formation of a minute trench even when the shoulder portion of the trench is backed off. Further, it is still another object to form the trench so as to contribute to enhancement of current capability of an insulting gate type field-effect transistor formed adjacent to the trench.